BORDEAUX, France — A European research program is starting work on designs in the areas of digital video broadcasting and industrial control. The program also plays a key role in helping Cadence Design Systems Inc. (San Jose, Calif.) develop tools to handle codesign of hardware and software under its Felix initiative.

Research groups at Philips (Eindhoven, Netherlands), Siemens (Munich, Germany) and Cadence European Labs (Rome), with support from commercial groups at the three companies, are teamed up to flesh out a design flow for system-level design based on reusable hardware and software intellectual property (IP).

The 30-month project, called Cosy (Codesign, Simulation and Synthesis), is intended to produce a complete system-level design environment by the end of 1999, together with libraries of appropriately characterized hardware and software IP modules. Integration and demonstration of completed designs and a pre-release of the Cosy environment is due in the first quarter of 2000.

Cosy is organized under the Open Microprocessor Systems Initiative (OMI) of Europe's Esprit program of collaborative research and technology development.

Jean-Yves Brunel, project leader in information-processing architectures at Philips Research, speaking here at the European Multimedia, Microprocessor Systems and Electronic Commerce conference, outlined the approach being taken by Cosy.

Brunel said the first year of the project, which began in October 1997, had been spent specifying the Cosy methodology. This is now completing, he said, and the work continues developing performance, function and interface models for virtual components relevant to the two applications together with the ability to cosimulate and cosyntheisize hardware and software.

Felix tools, which are currently being developed under the Virtual Component Codesign (VCC) label by Cadence, are a foundation of the project. The Felix project was made public by Cadence in December 1997. The participants include Ericsson, BMW, ARM Ltd., Debis Systemhaus, Magneti Marelli SpA, Motorola Semiconductor, National Semiconductor, STMicroelectronics and Symbionics Ltd., now part of Cadence. The initiative has been making use of research conducted by Cadence Berkeley Labs and Cadence European Labs, as well as the University of Torino (Italy) and the University of California at Berkeley.

Brunel said Cosy would use Felix tools from Cadence, Philips would apply them to the design of a system-on-a-chip decoder for digital video broadcast applications and Siemens would apply them to an industrial controller implemented using a rapid prototyping system based on an FPGA and DSP platform. As a part of its work, Brunel said he expected Cosy to contribute second-generation additions to the Felix tool set, such as software-authoring tools including scheduling tools and synthesis tools.

The development of thread-reducing tools had been highlighted as a key area, said Brunel. "Reducing the number of threads created when specifying the functionality of a system has a first-degree impact," he said.

However, at the beginning of the Cosy project developers will make use of existing Felix tools. "Felix already exists and is about to be announced. The project will be based on Felix and the principle that you separate behavior from architecture then map [behavior onto architecture] and refine," Brunel said. Cadence has officially said there are no immediate plans for a general launch of the Felix initiative's VCC products.

The Cosy project will use a variety of input languages to specify systems, including SDL — a specification and design language standardized by the International Telecommunications Union — C, C++ and Cadence's SPW. Brunel said that in particular Cosy would use SDL- - . "That's a subset of SDL that we can synthesize from," said Brunel. The creation of automatic synthesis tools to move from SDL to VHDL have been attempted in the past but have proved problematic.

Brunel said SDL- - and synthesis from it had been developed at Cadence Berkeley Labs.

Although Cosy will represent a step up in abstraction from current design practice, allowing design capture prior to partitioning into hardware and software, it will still depend on human partitioning. "The capture of the functional specification is human and the selection of the architecture is human," said Brunel.

Brunel said Cosy would also be used to evaluate Esterel-C, which is a combination of the Esterel language developed by a team under Gerard Berry of the Ecoles des Mines de Paris (Sophia Antipolis, France) and the general-purpose programming-language C.

"For Philips, one of the major deliverables is the library of IPs for digital video broadcasting," said Brunel, adding that it would include hardware cores and software algorithms. "We need a number of views, functional models and several implementation models." He pointed out that in digital video where Philips has deployed its TriMedia very long instruction word (VLIW) processor, it is important for the company to be able to estimate the impact of implementing video algorithms in dedicated hardware, on the VLIW processor or on a RISC processor.

On-chip bus interfacing will also be an important facet of the Cosy project. "A generic bus interface is very important. Our IPs in the project will be based on the VSI Alliance generic bus definition and the PI-bus."

The Peripheral Interconnect Bus is a standard on-chip bus developed by a consortium of European semiconductor companies under OMI although many have continued to use and develop proprietary on-chip buses, subsequently.

Brunel said the link to implementation would be done with Cadence's design services group based in Livingston, Scotland.