Publications 2011

International Conferences with Proceedings

Implementation of complex strategies of security in secure embedded systems

Robisson Bruno, Agoyan Michel, Le Henaff S, Soquet P, Phan G, Wajsbürt Franck, Bazargan Sabet Pirouz

IFIP International Conference on New Technologies, Mobility and Security (NTMS'2011), Paris, France, February 2011

773

Comparison Between Heterogeneous Mesh-based and Tree-based Application Specific FPGA

Farooq Umer, Parvez Husain, Marrakchi Zied, Mehrez Habib

International Symposium on Applied Reconfigurable Computing (ARC'2011), Belfast, United Kingdom, March 2011, pp. 218-229

787

NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs

Porquet Joël, Greiner Alain, Schwarz Christian

Design Automation and Test in Europe Conference (DATE'2011), Grenoble, France, March 2011, Grenoble, France, March 2011, pp. 591-594

[import file] 740

Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools

Belloeil-Dupuis Sophie, Chotin-Avot Roselyne, Mehrez Habib

International Symposium on Quality Electronic Design (ISQED'2011), Santa Clara, California, USA, March 2011, pp. 502-507

741

Management of the security in smart secure devices

Robisson Bruno, Agoyan Michel, Bouquet S, Nguyen Min-Huu, Le Henaff S, Soquet P, Phan G, Wajsbürt Franck, Bazargan Sabet Pirouz, Drach Nathalie

Smart Systems Integration Conference (SSI'2011), Zurich, Suisse, March 2011

743

Exploration of the Effect of LUT and Arity Size on a Tree-based Application Specific FPGA

Farooq Umer, Parvez Husain, Marrakchi Zied, Mehrez Habib

IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS'2011), Athens, Greece, April 2011, pp. 1-6

788

Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

Zhang Zhen, Refauvelet Dimitri, Greiner Alain, Benabdenbi Mounir, Pêcheux François

The 29th IEEE VLSI Test Symposium (VTS'2011), Dana Point, California, USA, May 2011

[import file] 778

Low-cost recovery for the code integrity protection in secure embedded processors

Nguyen Min-Huu, Robisson Bruno, Agoyan Michel, Drach Nathalie

IEEE International Symposium IEEE International Symposium on Hardware-Oriented Security and Trust (HOST'2011), San Diego, Etats-Unis, June 2011

774

Monitoring Software Communication Channels on a Shared Memory Multi-Processor System on Chip

Genius Daniéla, Pouillon Nicolas

Reconfigurable Communication-centric SoCs (ReCoSoC'2011), Montpellier, France, June 2011

777

A Complete methodology for determining memory BIST optimization under wrappers sharing constraints

Zaourar Lilia, Kieffer Yann, Wenzel Arnaud

4th Asia Symposium on Quality Electronic Design (asqed'2011), Kuala Lumpur, Malaysia, July 2011, pp. 46-53

782

A Global Optimization for Scan Chain Insertion at the RT-level

Zaourar Lilia, Kieffer Yann, Aktouf Chouki

IEEE Computer Society Annual Symposium on Emerging VLSI (ISVLSI'2011), Chennai, India, July 2011, pp. 321-322

781

A multi-objective optimization for memory BIST sharing using a genetic algorithm

Zaourar Lilia, Kieffer Yann, Wenzel Arnaud

17 International Symposium on International On-Line Testing Symposium (IOLTS'2011), 73-78, Athens, Greece, July 2011, pp. 73-78

780

Using runtime activity to dynamically filter out inefficient data prefetches

Gamoudi Oussama, Drach Nathalie, Heydemann Karine

European Conference on Parallel computing (Euro-Par'2011), Bordeaux, France, August 2011

775

Analog Circuits Sizing Using Bipartite Graphs

Javid Farakh, Iskander Ramy, Louërat Marie-Minerve, Dupuis Damien

Midwest Symposium on Circuits and Systems (MWSCAS'2011), Seoul, South Korea, August 2011, pp. 1-4

790

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

Zaourar Lilia, Kieffer Yann, Aktouf Chouki

IEEE 20th Asian Test Symposium (ATS'2011), New Delhi, India, November 2011

783

MORPHEO: a high-performance processor generator for a FPGA implementation

Rosière Mathieu, Desbarbieux Jean-Lou, Drach Nathalie, Wajsbürt Franck

IEEE International Conference on Design and Architectures for Signal and Image Processing (DASIP'2011), Tampere, Finlande, November 2011

776

Analyzing Software Inter-Task Communication Channels on a Clustered Shared Memory Multi Processor System-on-Chip

Genius Daniéla, Pouillon Nicolas

IEEE International Conference on Design and Architectures for Signal and Image Processing (DASIP'2011), Tampere, Finland, November 2011

791

International Conferences without Proceedings

Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs

Javid Farakh, Iskander Ramy, Louërat Marie-Minerve, Dupuis Damien

IEEE International Workshop on MOS Modeling and Parameter Extraction (MOS-AK'2011), Paris, France, April 2011

753

A Stack-Based Routing Methodology For Nanometric CMOS Devices

Youssef Stéphanie, Dupuis Damien, Iskander Ramy, Louërat Marie-Minerve

IEEE International Workshop on MOS Modeling and Parameter Extraction (MOS-AK'2011), Paris, France, April 2011

754

Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties

Iskander Ramy, Louërat Marie-Minerve

IEEE International Workshop on MOS-AK/GSA (MOS-AK'2011), Paris, France, April 2011

752

National Conferences without Proceedings

Etude du problème de partage de blocs BIST pour le test des mémoires.

Zaourar Lilia, Munier-Kordon Alix

12 congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF'2011), Saint Etienne, France, Mars 2011

784

Scientific Journals with Editorial Committee

A graph-based analysis of the cyclic scheduling problem with time constraints: schedulability and periodicity of the earliest schedule

Munier-Kordon Alix

Journal of Scheduling, 2011, vol. 14, num. 1, pp. 103-117, Springer

617

Approche pour l'intégration du raffinement formel dans le processus de conception des SOC

Mokrani Hocine, Ameur-Boulifa Rabea, Encrenaz Emmanuelle, Coudert Sophie

Journal Européen des Systèmes Automatisés, 2011 (à paraître)

792

Feasibility Analysis for Robustness Quantification by Symbolic Model Checking

Baarir Soheib, Braunstein Cécile, Encrenaz Emmanuelle, Ilié Jean-Michel, Mounier Isabelle, Poitrenaud Denis, YOUNES Sana

Formal Methods in System Design, 2011 (à paraître)

793

A general analytical tool for the design of Vibration Energy Harvesters (VEH) based on the mechanical impedance concept

Galayko Dimitri, Basset Philippe

IEEE Transactions on Circuits and Systems: I, Feb. 2011, vol. 58, num. 2, pp. 299-311, IEEE

742

Exploration of Heterogeneous FPGA Architectures

Farooq Umer, Parvez Husain, Marrakchi Zied, Mehrez Habib

International Journal of Reconfigurable Computing , Feb. 2011, num. 2011

786

Feasibility Analysis for Robustness Quantification by Symbolic Model Checking

Baarir Souheib, Braunstein Cécile, Encrenaz Emmanuelle, Li Tun, Mounier Isabelle, Poitrenaud Denis, YOUNES Sana

Formal Methods in System Design, June 2011

785

Contributions to Books

Mapping a Telecommunication Application on a Multiprocessor System-on-Chip

Genius Daniéla, Faure Etienne, Pouillon Nicolas

Algorithm-Architecture Matching for Signal and Image Processing, chap. 1, pp. 53-77, (edited by : Gogniat, G et al.), Springer LNEE vol. 73, November 2011

719

Thesis

“ON THE FIELD” DETECTION, DEACTIVATION & RECONFIGURATION (ODDR) MECHANISM FOR PERMANENT FAULT-TOLERANCE OF NETWORK-ON-CHIP

Zhang Zhen

Thèse de l'Université Pierre et Marie Curie, 27/06/2011

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