The Coriolis platform

Coriolis is an experimental integrated platform for the research, development and evaluation of new back-end VLSI design flows. Interconnect scaling to nanometer processes presents many difficult challenges to CAD flows. Currently academic research on back-end tend to address only specific algorithmic issues separately, although one key issue to address is the cooperation of multiple algorithmic tools. CORIOLIS, our platform, is based on an integrated C++ database around which all tools consistently interact and collaborate. This platform currently includes a timing-driven global place and route flow.

The Coriolis flow

The flow developed and under experimentation is a top-down refinement process which proceeds by a succession of interleaved phases of quadri-partitioning, global routing and net-list timing optimizations:

The entry point is the geometric quadri-partitioning of all bins with more than, let say, 100 instances. Then the net-lists of those bins are quadri-partitioned (independently but taking into account pseudo-pins and net criticalities, if already available from a previous iteration).

Then the global router (re)builds or refines the steiner-trees of all nets whose cells have changed location. It has multiple algorithmic tactics tailored for different net configuration and criticalities, and tries to both minimize wire length and congestion on fences.

After this step, the RC trees are (re)evaluated and a new static timing analysis is processed in order to compute critical paths, slacks and criticality value on each arc of the timing graph which provide tighter directives to the next placement and global routing step.

At this step, data is available to proceed (in the future) to gate sizing and buffer planning (buffers will be virtually inserted in the timing graph, not in the net-list, and corresponding area requirement reserved in the bins). This will require of course an engine to spread apart cells and maintain area density in the bins.

Once this refinement loop ends, buffers are physically created in the net-list, the detailed placement step legalize and fixes precisely cell locations. Then additional steps of global routing refinement can proceed, taking into account pin locations and obstructions. After a last pass of timing analysis, the resulting global routing directives and net criticalities can be fed to a detail router (under development).

See below a screenshot of the Coriolis platform in action.

screenshot

Publications

« TSUNAMI : an Integrated Timing-Driven Place and Route Research Platform » (Coriolis was formerly named Tsunami), C. Alexandre, H. Clément, J.-P. Chaput, C. Masson, R. Escassut, DATE'05 in München, March 2005.

The Coriolis team

Core team

Christophe Alexandre, PhD student, Project founder,Christophe.Alexandre@lip6.fr.
Hugo Clément, PhD student, Project founder, Hugo.Clement@lip6.fr.
Jean-Paul Chaput, Research engineer, Project founder, Jean-Paul.Chaput@lip6.fr.
Christian Masson, Senior research advisor, Christian.Masson@lip6.fr.
Marek Sroka, PhD student, Marek.Sroka@lip6.fr.
Damien Dupuis, PhD student, Damien.Dupuis@lip6.fr.

Contributors

Sophie Belloeil, PhD student, Sophie Belloeil@lip6.fr.


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