Advanced Architecture and Compiler for High-Performance Embedded Processors

Under Construction

Team

Nathalie Drach : Professor UPMC

François Anceau : Professor CNAM

Alexandre Coveliers : PhD Student

Maxime Palus : PhD Student

Mathieu Rosière : PhD Student

Research topics

Our purpose is to develop or/and to adapt architecture and program optimization techniques for the high performance needs of embedded processors.

• Processor architecture : java-processor, simultaneous multithreading processor, multiprocessor on-chip, data-flow (desynchronized super-scalar) processors.
• Program optimizations and compilation: platform for iterative compilation, iterative compilation by simulation.
• Computer architecture simulation and methodology.
• Impact of new technologies on computer architecture/compilation/programming.

Collaborations (recent)

Member of Hipeac NoE (2004-2008).

Member of ACN NanoSys (2004-2007).

Project RNTL COP (2004-2006).

Leader of the CNRS-AS New technologies (2002-2003). Member of CNRS-AS SOC New technologies (2003-2004). Member of CNRS-AS Architecture and Operating System Architecture (2003-2004). Member of steering committee of CNRS-RTP Architecture and Compilation (2002-2004).

Project RNTL ATLAS (2002-2004).