Cécile's Research

Research Interests :

Keywords : Formal Methods, Model Checking, Bounded Model Checking, SAT techniques, Diagnosis, Abstraction, Refinement, CEGAR, VLSI, VHDL,Hardware Architecture

Publications :

"CTL-Property transformation along an Incremental Design Process ", C. Braunstein and E. Encrenaz, International Journal on Software Tools for Technology Transfer, 2006 STTT. ; the proof of theorem 1

"Increasing the Accuracy of SAT-Based Debugging ", André Suelflow, Görschwin Fey, Cécile Braunstein, Ulrich Kuehne, Rolf Drechsler, Design Automation and Test in Europe Conference DATE'2009 , April 2009.

"Using CTL formulae as component abstraction in a design and verification flow", C. Braunstein and E. Encrenaz, 7th International Conference on Application of Concurrency to System Design, ACSD'07 , 2007.

"Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter ", C. Braunstein and E. Encrenaz, 17h IEEE/IFIP International Workshop on Rapid System Prototyping RSP'06, Chania, Greece, June 2006.

"CTL-Property Transformation along an incremental Design Process", C. Braunstein and E. Encrenaz, Proceedings of the 4th International Workshop on Automated Verification of Critical Systems, AVOCS'04, ENTCS (128), pages 263-278, London, England, September 2004. (Slides )

"A Further Step in the Incremental Design Process: Incorporation of an Increment Specification", C. Braunstein and E. Encrenaz, short paper Proceedings online of the 13th Conference Logic for Programming Artificial Intelligence and Reasoning, LPAR'06 September 2006. (Slides )

"Conception Incrémentale, Vérification de Composants Matériels et Méthode d'Abstraction pour Vérification de Systèmes Intégrés sur Puce ", C. Braunstein, 14th May 2007. (Slides )