Opened 18 years ago

Last modified 18 years ago

#2 new task

Generation de VHDL

Reported by: Nicolas Pouillon Owned by: Nicolas Pouillon
Priority: major Milestone:
Component: codegen-soclib Version:
Keywords: Cc:

Description

Generer le toplevel VHDL pour simulation/synthese

  • Besoin des composants endeveloppement

Change History (3)

comment:1 Changed 18 years ago by Nicolas Pouillon

SocLib's not ready yet, I'll put in a framework for RTL (Vhdl/Verilog?) netlist generation, but it wont be complete, and there will not be any component description

comment:2 Changed 18 years ago by Nicolas Pouillon

Milestone: Fin stage sept 2006 → milestone2

Deferred ditto

comment:3 Changed 18 years ago by Nicolas Pouillon

Milestone: milestone2

Milestone milestone2 deleted

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