Changes between Version 4 and Version 5 of DsxArchitectureCreation

Timestamp:

Feb 14, 2007, 10:00:46 PM (18 years ago)

Author:

Nicolas Pouillon

Comment:

--

DsxArchitectureCreation

@@ -1 +1 @@
 = Generic Architectures =
+
+[[PageOutline]]
 
 == The concept ==
@@ -37 +39 @@
 
         # Cache ports connexion
-        cache0.cache( mips0.cache ) 
-        vgmn.getTarget()( cache0.vci ) 
+        cache0.cache // mips0.cache
+        vgmn.getTarget() // cache0.vci
 
         reset = Segment( ’reset’, 
                          address = 0xbfc00000, 
                          type = Cached ) 
+        excep = Segment( ’excep’, 
+                         address = 0x80000080, 
+                         type = Cached ) 
         code = Segment( ’code’, type = Cached ) 
         data = Segment( ’data’, type = Uncached ) 
-        ram = MultiRam( ’ram’, reset, code, data ) 
+        ram = MultiRam( ’ram’, reset, excep, code, data ) 
 
         # Connections
-        vgmn.getInit()( ram.vci ) 
+        vgmn.getInit() // ram.vci
 
         # Declare base component
-        self.setBase( vgmn ) 
+        self.setBase(vgmn)
 
         # Add configuration utilities
@@ -68 +73 @@
 
 We will define a one-level architecture using a Vgmn, with two parameters: number of Cpus (`ncpu`) and number of Ram components (`nram`).
-By default, we will set `nram` to 1.
+We will set `nram` default value to 1.
 
-We'll add in ram0 (which always exists) two more segments.
+We'll add in `ram0` (which always exists) two more segments: `excep` and `reset`.
 
-We'll set those attributes:
+We'll those attributes in instance objet (accessible through `object.name`):
  * `vgmn`: the interconnect
- * `cpu`: an array of all the cpus
- * `ram`: an array of all the ram chips
- * `cram`: an array of all the cached ram segments
- * `uram`: an array of all the uncached ram segments
+ * `cpu`: a list of all the cpus
+ * `ram`: a list of all the ram chips
+ * `cram`: a list of all the cached ram segments
+ * `uram`: a list of all the uncached ram segments
 
 This way, we'll be able to refer to `platform.ram[2]` or `platform.cpu[0]`.
@@ -95 +100 @@
 
             # Cache ports connexion
-            cache.cache( cpu.cache ) 
-            vgmn.getTarget()( cache.vci )
+            cache.cache // cpu.cache
+            vgmn.getTarget() // cache.vci
             self.cpu.append( cpu )
 
@@ -107 +112 @@
             ram = MultiRam( ’ram%d’%i, cram, uram)
 
-            vgmn.getInit()( ram.vci )
+            vgmn.getInit() // ram.vci
             self.ram.append( ram )
             self.cram.append( cram )
@@ -121 +126 @@
         self.setConfig(’mapping_table’, MappingTable())
 }}}
+
+In this platform
+ * argument `nram` is optional with default value being 1
+ * arguments `ncpu` is mandatory