Changes between Version 10 and Version 11 of DsxDocumentation

Timestamp:

Jan 28, 2008, 6:35:17 PM (17 years ago)

Author:

alain

Comment:

--

DsxDocumentation

@@ -81 +81 @@
 footprint is reduced, at the cost of loosing the POSIX compatibility. 
 
-== C)  Defining the software application ==
+== C)  Software application definition ==
 
 This section describes the DSX/L syntax used to define the Task & Communication Graph structure.
@@ -96 +96 @@
 As a software application can instanciate several instances of the same task, we must distinguish the task, and the task model. A task model defines the code associated to the task, and the task interface (corresponding to the system resources used by the task : MWMR communications channels, synchronization barriers, locks, and memspaces).
 {{{
-Task_Model = TaskModel( 'model_name',
+task_model = TaskModel( 'model_name',
                     infifos = [ 'inport_name', ... ] ,
                     outfifos = [ 'outport_name', ... ] ,
@@ -122 +122 @@
 For performances reasons the channel ''width'' itself must be a multiple of 4 bytes.
 {{{  
-My_Channel = Mwmr( 'channel_name', width, depth )
+my_channel = Mwmr( 'channel_name', width, depth )
 }}}
 In the mapping section of the DSX/L program, the 4 following software objects must be placed :
@@ -136 +136 @@
 is defined when the the tasks are intanciated. Exclusive access to the barrier is protected by an implicit lock.
 {{{
-My_Barrier = Barrier( 'barrier_name' )
+my_barrier = Barrier( 'barrier_name' )
 }}}
 In the mapping section of the DSX/L program, the 3 following software objects must be placed :
@@ -149 +149 @@
 the number of bytes to be reserved.
 {{{
-My_Shared_Buffer = Memspave( ''memspace_name', size )
+my_buffer = Memspace( ''buiffer_name', size )
 }}}
 In the mapping section of the DSX/L program, the 2 following software objects must be placed :
@@ -161 +161 @@
 has been obtained.
 {{{
-My_Lock = Lock( 'lock_name' )
+my_lock = Lock( 'lock_name' )
 }}}
 In the mapping section of the DSX/L program, the lock can be explicitely placed in the memory space. 
@@ -170 +170 @@
 ''Task_Model'' (created by the TaskModel() function), and a list of resources (MWMR channels, synchronization barriers, locks or memspaces), that must be associated to the task ports. DSX performs type checking between the port name and the associated resource.
 {{{
-My_Task = Task( 'task_name',
-                         Task_Model ,
-                         portmap = { 'port_name' : My_Channel, 'barrier_name' : My_Barrier, ... } )
+my_task = Task( 'task_name',
+                         task_model ,
+                         portmap = { 'port_name' : my_channel, 'barrier_name' : my_barrier, ... } )
 }}}
 In the mapping section of the DSX/L program, 4 software objects must be placed :
@@ -184 +184 @@
 The Task and Communication Graph must be defined :  
 {{{
-My_Tcg = Tcg( 
+my_tcg = Tcg( 
              Task(  'task_name1, 
                      Task_Model1, 
@@ -194 +194 @@
 }}}
 
-== D)  Defining the hardware architecture ==
+== D)  Hardware architecture definition ==
 
 This section describes the DSX/L syntax used to define the MP-SoC hardware architecture,
 using the hardware components defined in the SoCLib library.
 
-=== D1) SoCLib components definition ===
+=== D1) SoCLib components  ===
 
 In the present version of DSX, each hardware component must be described by a PYTHON
@@ -207 +207 @@
 {{{
 # creation of a MIPS R3000 processor core
-My_Proc = Mips( 'proc' )
+my_proc = Mips( 'proc' )
 
 # creation of a cache controler
-My_Cache = Xcache( 'cache',
+my_Cache = Xcache( 'cache',
                         dcache_lines = 32,
                         dcache_words = 8,
@@ -220 +220 @@
 
 Hardware components have input/output ports, and are connected through signals, 
-but those signals are implicit in the DSX/L description. To connect the port a of component c1 to the port b of component c2, DSX/L define the // operator : 
+but those signals are implicit in the DSX/L description. To connect the port '''a''' of component '''c1''' to the port '''b''' of component '''c2''', DSX/L define the // operator : 
 {{{
 c1.a // c2.b
@@ -230 +230 @@
 {{{
 # components instanciacion
-My_Proc0 = Mips( 'proc0' )
-My_Cache0 = Xcache( 'cache0' )
-My_Proc1 = Mips( 'proc1' )
-My_Cache1 = Xcache( 'cache1' )
-My_Ram = MultiRam( 'ram' )
-My_Crossbar = LocalCrossbar( 'crossbar' )
+my_Proc0 = Mips( 'proc0' )
+my_Cache0 = Xcache( 'cache0' )
+my_Proc1 = Mips( 'proc1' )
+my_Cache1 = Xcache( 'cache1' )
+my_Ram = MultiRam( 'ram' )
+my_Crossbar = LocalCrossbar( 'crossbar' )
                      
 # components connexion
-My_Proc0.cache // My_Cache0.cache
-My_Proc1.cache // My_Cache1.cache
-My_Crossbar.getTarget() // My_cache0.vci
-My_Crossbar.getTarget() // My_cache1.vci
-My_Crossbar.getInitiator() // My_cache0.vci
-
-
+my_proc0.cache // my_cache0.cache
+my_proc1.cache // my_cache1.cache
+my_crossbar.getTarget() // my_cache0.vci
+my_crossbar.getTarget() // my_cache1.vci
+my_crossbar.getInitiator() // my_cache0.vci
 }}}
 }}}
@@ -250 +248 @@
 === D3) Address space segmentation ===
 
+All hardware components defining the hardware architecture should be grouped in a single object.
+As any MP-SoC architecture build with the SoCLib library uses a VCI interconnect hardware component,
+this component must be declared as the ''root'' of the architecture :
+{{{
+my_architecture = Hardware( vgmn )
+}}}
+
+In any shared memory architecture, the address space is a shared resource.  This resource is structured in several segments. A segment has a name, a base address, a size 
+(number of bytes), and a cacheability attribut (Boolean). A segment is a physical entity associated to a 
+given VCI target. Several segments can be associated to the same VCI target, but a given segment cannot be distributed over several VCI targets.
+
+The DSX/L language allows the system designer to define the various segments used by a given application,
+and to link those segments to the hardware components.
+The base address and the segment size are optional parameters :
+{{{
+# segments definition
+seg_data1 = Segment( 'seg1', Cached )
+seg_data2 = Segment( 'seg2', Uncached )
+seg_reset = Segment( 'reset', Cached, addr = 0xBFC00000 )
+
+# Instanciating a VCI target hardware component
+# and Linking  the segments to this component
+my_ram = MultiRam ( 'ram', seg_data1, seg_data2, seg_reset )
+}}}
+
+As a segment is defined by the MSB bits of the VCI address, the hardware interconnect must decode those MSB bits to select the proper VCI target. The corresponding decoder is generally  implemented as a ROM. Those hardware decoders are automatically constructed using the '''Mapping Table'''. The mapping table is 
+an associative table. Each entry corresponds to a physical segment. This object must be constructed, and initialised:
+{{{
+# mapping table construction
+my_mt = MappingTable()
+# mapping table initialisation
+my_hardware.setConfig( 'maptab', my_mt )
+}}}
+ 
+
 === D4) Hardware architecture definition ===
 
+
 === D5) Mapping table ===