15 | | The software application must be statically defined as a '''Task & Communications Graph'''. |
16 | | The number of tasks (defining the coarse grain parallelism), and the communication channels between |
17 | | tasks should not change during execution. The two targeted application domains are the telecommunication |
18 | | applications (where the tasks are handling packets or packet descriptors), and multi-media applications |
19 | | (where the tasks are handling audio or video streams). |
20 | | |
21 | | A specific goal of DSX is to allow the system designer to control not only the the placement of the |
22 | | tasks on the processors, but also to control precisely the placement of the software objects (execution stacks, |
| 15 | A specific goal of DSX is to allow the system designer to control not only the placement of the |
| 16 | tasks on the processors, but the placement of the software objects (execution stacks, |
33 | | DSX/L is a language based on PYTHON, that allows the system designer to describe : |
34 | | * the Task & Communication Graph (TCG) |
35 | | * the MP-SoC hardware architecture (using the hardware components available in SoCLib). |
36 | | * the mapping of the TCG on the MP-Soc architecture. |
| 23 | The general principles of the DSX tool are the following: |
| 24 | * The coarse grain parallelism of the software application must be statically defined as a '''Task & Communications Graph (TCG)'''. The number of tasks, and the communication channels between tasks should not change during execution. |
| 25 | * The software tasks are supposed to be written in C or C++, but - for portability reasons - the tasks must use an abstract '''System Resource Layer (SRL)''' API to access the communication and synchronizations resources. |
| 26 | * Each task in the TCG can be implemented as a ''software task'' (software running on an embedded processor), or can be implemented as an ''hardware task'', (running as a dedicated hardware coprocessor). |
| 27 | * DSX allows the programmer to use unprotected shared memory spaces, but the prefered inter-tasks communication mechanism use the MWMR middleware. The MWMR (Multi-Writer, Multi-Reader) channels, are implemented as software FIFOs and can be shared by ''software tasks'', and by ''hardware tasks. |
| 28 | * DSX provides classical synchronization mechanisms such as barriers and locks, but inter-task synchronisation is mainly done through the data availability in the MWMR channels. |
| 29 | * The target hardware architecture is a shared memory multi-processor system on chip (MP-SoC) using the SoCLib library of IP cores. But - in order to validate the multi-threaded software application - DSX is able to generate an executable binary code for a standard POSIX workstation. |
| 30 | * DSX supports the POSIX compliant [https://www-asim.lip6.fr/trac/mutekh Mutek] OS kernel for embedded MPSoCs |
| 31 | * Finally, DSX defines the DSX/L language, based on PYTHON, that allows the system designer to describe in a single file the Task & Communication Graph (TCG), the MP-SoC hardware architecture, and various mapping of the TCG on the MP-Soc architecture. |