Changes between Version 17 and Version 18 of SoclibComponents

Timestamp:

Jan 28, 2008, 4:20:57 PM (17 years ago)

Author:

alain

Comment:

--

SoclibComponents

@@ -1 +1 @@
 [[PageOutline]]
 
-= Interconnects =
+= A) Interconnects =
 
-== Vgmn ==
+== A.1) Vgmn ==
 
  * functionality : a generic VCI compliant micro-network
@@ -17 +17 @@
    * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand
 
-== !LocalCrossbar ==
+== A.2) !LocalCrossbar ==
 
  * functionality : a VCI compliant crossbar interconnect
@@ -30 +30 @@
    * `upstream`, bidirectional port to upper-level interconnect
 
-= VCI Initiators =
+= B) VCI Initiators =
 
-== Xcache ==
+== B.1) Xcache ==
 
  * functionality: a direct mapping cache controler (separated instruction & data cache)
@@ -54 +54 @@
    * `vci`: to the VCI micro-network
 
-= Processors =
+= C) Processors =
 
-== Mips ==
+== C.1) Mips ==
 
  * Functionality : a MIPS R3000 micro-processor
@@ -69 +69 @@
    * `irq[n]`: interrupt line (0 <= n < 6)
 
-= VCI Targets =
+= D) VCI Targets =
 
-== !MultiRam ==
+== D.1) !MultiRam ==
 
  * !Mandatory arguments:
@@ -84 +84 @@
    * `vci`: to the micro-network
 
-== !MultiTty ==
+== D.2) !MultiTty ==
 
  * functionality: a TTY controler (up to  256 TTYs)
@@ -98 +98 @@
    * `irq[n]`: interrupt line (0 <= n < nb of ttys)
 
-== Locks ==
+== D.3) Locks ==
 
  * functionality : a locks controler